UPDATED: 31st May 2007
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Embedded Systems Laboratory
Department of Engineering
University of Leicester
University Road
Leicester
LE1 7RH
United Kingdom
T: +44 116 252 2578
F: +44 116 252 2619
The current version 2.0a of the PH Processor is described on this page.
PLEASE NOTE: This page describes a processor containing PH 2.0a core. The PH 2.0a core is available for free download for non-commercial use. An enhanced version of this core (PH core 3.0) is available for commercial use from TTE Systems limited. The PH 3.0 core includes enhanced debug support (including support for JTAG debugging and enhanced timing analysis). Please contact TTE Systems for further details of the PH 3.0 core.
The table below outlines the feature differences between the Free Non-Commercial core and the TTE Systems core
| Feature |
 PH Core 3.0 |
PH Core 2.0a |
|---|---|---|
| Board Support | Spartan-3 Board | Spartan-3 Board |
| Interface | USB or Parallel JTAG | RS232 Serial |
| Debug | Full GDB support through
 |
Basic VB GUI, single stepping no breakpoints |
| IDE | |
Visual Studio linked through GCC |
| Development Tools |
pattern based ultra fast development tool |
None |
| Support |
|
No support |
| License | Commercial | Free non-commercial only |
Please visit TTE Systems Limited
The design of this processor follows the outline provided by Patterson and Hennessy (2004). Briefly, the PH Processor is a 32-bit design with 32 registers and a 5-stage pipeline. The processor also includes a multiplier and divider and a cut down version of the system coprocessor CP0.
Please note that the 5-stage pipeline used closely resembles the setup describe by Patterson and Hennessy (2004), with one exception. As discussed by Charles Brej with the Yellow Star implementation, the ID (Instruction Decode) and WB (Write Back) stages are shrunk to half a cycle to allow conditional branch instructions to use the most recent forwarded values in the EX stage and update the PC before the next clock cycle, whilst maintaining a one-branch delay slot.
The data and control paths also closely resemble the setup describe by Patterson and Hennessy, but with the addition of extra logic units and data/control paths to support all integer non-patented MIPS I™ instructions. External interrupts are also supported through co-processor zero the system coprocessor.
A clearer view of the data and control paths can be seen here.
A report containing implementation details can be read here.
MIPS® is a registered trademark and MIPS I™ is a trademark of MIPS Technologies, Inc. in the United States and other countries. MIPS Technologies, Inc. does not endorse and is not associated with this project, and we are not affiliated in any way with MIPS Technologies, Inc.
Our current implementation of the PH processor was created using VHDL with Xilinx ISE tools targeting a Xilinx 200K gate or 1000K Spartan 3 FPGA chip on a Digilent Spartan 3 development board.
On the 200K gate version there are 216KBits of block RAM on the chip and 1MB of SRAM on-board. The board contains a serial port, led's, seven segment display, buttons and switches and costs about £60 (UK pounds).
We have developed a PC application which allows the PH Processor to be programmed and debugged using a serial link between the PC and the FPGA board. In this way the user can monitor everything down to the control and data paths.
The BL (Buttons and Lights) block is a peripheral that connects to the onboard LEDs, buttons and seven-segment display. The timer is attached on the data bus where the necessary registers are easily addressed through normal memory load and store instructions.
(We say a more about this debug application here)
All non-patented, integer, MIPS I™ instructions are supported. To ensure that patented instructions are not used by the compiler all words must be word aligned. (There are a number of patches to the GNU GCC compiler which can enforce this - see next section).
An instruction set table of the implemented instructions can be viewed here.
Programs can be compiled and assembled using a MIPS® port of GNU GCC and GNU Binutils. We are currently using the SDE-Lite GCC tools available from MIPS Techonolgies.
The output of the assembled, compiled and linked process is an ELF 32 format object file, so a program 'ZCV' was written to extract the binary data of the text and data segments into two binary files called 'code.bin' and 'data.bin'.
The ZCV program can be downloaded here.
Below lists some example compiler options used, you may need to change directory paths:
The makefile for the processor can be seen in the example C code available in downloads.
The example C code used is a port of the co-operative scheduler developed by Pont (2001) and is used to flash the on-board LEDs.
The two files created from the compilation process above are loaded into the onboard instruction and data RAMs at address zero and address 0x10000 respectively via a Visual Basic debug program (using the serial port). The instruction memory window is updated with a (disassembled) view of the program loaded into the instruction RAM. The data memory window is updated with the contents of the data RAM. Once loaded the processor must be reset by clicking the reset button before trying to run or single step the code.
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When single stepping through the program the assembly instructions, data path and a few key control values are updated. This system is useful to check modifications and new instructions added to the processor are operating as intended.
The version of the PH Processor described here (and the related tools) were developed by Zemian Hughes as part of his PhD project in the ESL. Zemian's PhD supervisors are Michael J. Pont and Royan Ong.
We are extremely grateful to Prof. David Patterson (University of California Berkeley) and Prof John Hennessy (Stanford University) - and Elsevier (their publishers) for permission to release the code for the PH Processor. If you use this processor, please buy a copy of Patterson and Hennessy (2004) - it's a great book!
For the commercial PH Core 3.0 please contact:
Other processor cores which may be of interest:
Patterson, D.A. and Hennessy, J. L. (2004) "Computer Organization and Design: The Hardware/Software Interface", (3rd Edition). Elsevier / Morgan-Kaufmann. ISBN: 1-55860-604-1
Pont, M.J. (2001) "Patterns for time-triggered embedded systems: Building reliable applications with the 8051 family of microcontrollers", ACM Press / Addison-Wesley. ISBN: 0-201-331381.
We've tried to keep this as simple as possible.
The PH Processor and related programs and documentation may be used without charge for commercial and non-commercial use as long as the author and disclaimer notices are maintained.
Sorry - you're on your own (we cannot provide support).
If you find a bug that is not on the bug list, please send Zemian an e-mail (contact details below).
The PH Processor is solely intended for use in university teaching and research projects.
All of this material is provided "as is" and any express or implied warranties, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose are disclaimed. In no event shall the author or contributors be liable for any direct, indirect, incidental, special, exemplary, or consequential damages (including, but not limited to, procurement of substitute goods or services; loss of use, data, or profits; or business interruption) however caused and on any theory of liability, whether in contract, strict liability, or tort (including negligence or otherwise) arising in any way out of the use of this software, even if advised of the possibility of such damage.
NOTE: By downloading, you signify that you accept the disclaimer (above).
Available files include: